SH7014 Datasheet, PDF (652/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
DMAC
Bit
13, 12
Name
Source Address Mode 1, 0
(SM1 and SM0)
11 to 8 Resource Select 3 to 0
(RS3 to RS0)
6
DREQ Select (DS)
5
Transfer Mode (TM)
4, 3 Transfer Size 1, 0 (TS1, TS0)
2
Interrupt Enable (IE)
Value
0
0
1
1
0
1
0000
1
10
1
100
1
10
1
1000
1
10
1
100
1
10
1
0
1
0
1
0
0
1
1
0
1
0
1
Description
Source address fixed
(initial value)
Source address incremented (+1 during 8-bit
transfer, +2 during 16-bit transfer, +4 during
32-bit transfer)
Source address decremented (–1 during 8-bit
transfer, –2 during 16-bit transfer, –4 during
32-bit transfer)
(Setting prohibited)
External request, dual address mode
(initial value)
(Prohibited)
External request, single address mode.
External address space → external device.
External request, single address mode.
External device → external address space.
Auto-request
(Prohibited)
MTUTGI0A
MTUTGI1A
MTUTGI2A
(Prohibited)
(Prohibited)
A/D ADI
SCI0TXI0
RXI0
SCI1TXI1
RXI1
Low-level detection
(initial value)
Falling-edge detection
Cycle steal mode
(initial value)
Burst mode
Specifies byte size (8 bits)
(initial value)
Specifies word size (16 bits)
Specifies longword size (32 bits)
(Prohibited)
Interrupt request not generated after
DMATCR—specified transfer count
(initial value)
Interrupt request enabled on completion of
DMATCR specified number of transfers
Rev.5.00 Sep. 27, 2007 Page 618 of 716
REJ09B0398-0500