SH7014 Datasheet, PDF (160/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.3.3 CS Assert Period Extension
Idle cycles can be inserted to prevent extension of the RD signal or WRx signal assert period
beyond the length of the CSn signal assert period by setting the SW3 to SW0 bits of BCR2. This
allows for flexible interfaces with external circuitry. The timing is shown in figure 8.6. T_h and T_f
cycles are added respectively before and after the ordinary cycle. Only CSn is asserted in these
cycles; RD and WRx signals are not. Further, data is extended up to the T_f cycle, which is
effective for gate arrays and the like, which have slower write operations.
T_h
CK
T₁
T₂
T_f
Address
Read
CSn
RD
Data
Write
WRx
Data
DACK
Figure 8.6 CS Assert Period Extension Function
Rev.5.00 Sep. 27, 2007 Page 126 of 716
REJ09B0398-0500