SH7014 Datasheet, PDF (189/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Direct Memory Access Controller (DMAC)
Bit 18⎯Request Check Level (RL): Selects whether to output DRAK notifying external device
of DREQ received, with active high or active low.
Bit 18
RL
0
1
Description
Output DRAK with active high
Output DRAK with active low
(initial value)
Bit 17⎯Acknowledge Mode (AM): In dual address mode, selects whether to output DACK in
the data write cycle or data read cycle. In single address mode, DACK is always output
irrespective of the setting of this bit.
Bit 17
AM
0
1
Description
Outputs DACK during read cycle
Outputs DACK during write cycle
(initial value)
Bit 16⎯Acknowledge Level (AL): Specifies whether to set DACK (acknowledge) signal output
to active high or active low.
Bit 16
AL
0
1
Description
Active high output
Active low output
(initial value)
Bits 15 and 14⎯Destination Address Mode 1, 0 (DM1 and DM0): These bits specify
increment/decrement of the DMA transfer destination address. These bit specifications are ignored
when transferring data from an external device to address space in single address mode.
Bit 15
DM1
0
1
Bit 14
DM0
0
1
0
1
Description
Destination address fixed
(initial value)
Destination address incremented (+1 during 8-bit transfer, +2
during 16-bit transfer, +4 during 32-bit transfer)
Destination address decremented (−1 during 8-bit transfer, −2
during 16-bit transfer, −4 during 32-bit transfer)
Setting prohibited
Rev.5.00 Sep. 27, 2007 Page 155 of 716
REJ09B0398-0500