SH7014 Datasheet, PDF (163/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.4.3 Wait State Control
Wait state insertion during DRAM space access is controlled by setting the TPC, RCD, DWW1,
DWW0, DWR1, and DWR0 bits of the DCR. TPC and RCD are common to both reads and
writes. The timing with waits inserted is shown in figures 8.8 through 8.11. External waits can be
inserted at the time of software waits 2, 3. The sampling location is the same as that of ordinary
space: at one cycle before the T_c2 cycle clock rise. Wait cycles are extended by external waits.
T_p
T_r
T_c1
T_cw1
T_c2
CK
Address
Row
Column
Data
Write
RAS
CASx
RDWR
Read
Data
RAS
CASx
RDWR
Figure 8.8 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, One Wait)
Rev.5.00 Sep. 27, 2007 Page 129 of 716
REJ09B0398-0500