SH7014 Datasheet, PDF (381/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Serial Communication Interface (SCI)
1
Serial
data
TDRE
Start
bit
0 D0
Multiprocessor
bit
Stop Start
Data
bit bit
D1 D7 0/1 1 0 D0
Multiprocessor
bit
Stop
Data
bit
1
D1
D7 0/1 1
Idle
(marking
state)
TEND
TXI
interrupt
request
TXI interrupt
handler writes
data in TDR and
clears TDRE to 0
TXI
interrupt
request
TEI
interrupt
request
1 frame
Example: 8-bit data with multiprocessor bit and one stop bit
Figure 12.11 SCI Multiprocessor Transmit Operation
Receiving Multiprocessor Serial Data: Figures 12.12 (1) and (2) show a sample flowchart for
receiving multiprocessor serial data. The procedure for receiving multiprocessor serial data is
listed below.
1. SCI initialization: Set the RxD pin using the PFC.
2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1.
3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that
RDRF is set to 1, then read data from the receive data register (RDR) and compare with the
processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear
RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
bits in SSR to identify the error. After executing the necessary error processing, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data
from the receive data register (RDR).
Rev.5.00 Sep. 27, 2007 Page 347 of 716
REJ09B0398-0500