SH7014 Datasheet, PDF (201/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Direct Memory Access Controller (DMAC)
CK
A21 to A0
CSn
D15 to D0
WRH
WRL
DACK
Address output to external memory space
Data that is output from the external
device with DACK
WR signal to external memory space
DACK signal to external devices with
DACK (active low)
a. External device with DACK to external memory space
CK
A21 to A0
CSn
D15 to D0
RD
Address output to external memory space
Data that is output from external memory space
RD signal to external memory space
DACK
DACK signal to external device with DACK
(active low)
b. External memory space to external device with DACK
Figure 9.4 Example of DMA Transfer Timing in the Single Address Mode
Dual Address Mode: Dual address mode is used for access of both the transfer source and
destination by address. Transfer source and destination can be accessed either internally or
externally. In dual address mode, data is read from the transfer source during the data read cycle,
and written to the transfer destination during the write cycle, so transfer is conducted in two bus
cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external
memory transfer shown in figure 9.5, data is read from one of the memories by the DMAC during
a read cycle, then written to the other external memory during the subsequent write cycle. Figure
9.6 shows the timing for this operation.
Rev.5.00 Sep. 27, 2007 Page 167 of 716
REJ09B0398-0500