SH7014 Datasheet, PDF (510/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. I/O Ports (I/O)
Table 17.1 Port A
ROM Disabled Extended
Mode (Modes 0, 1)
ROM Enabled Extended
Mode (Mode 2)*
PA15 (I/O)/CK (output)
PA15 (I/O)/CK (output)
RD (output)
PA14 (I/O)/RD (output)
WRH (output)
PA13 (I/O)/WRH (output)
WRL (output)
PA12 (I/O)/WRL (output)
CS1 (output)
PA11 (I/O)/CS1 (output)
CS0 (output)
PA10 (I/O)/CS0 (output)
PA9 (I/O)/TCLKD
(input)/IRQ3 (input)
PA9 (I/O)/TCLKD (input)/
IRQ3 (input)
PA8 (I/O)/TCLKC
(input)/IRQ2 (input)
PA8 (I/O)/TCLKC (input)/
IRQ2 (input)
PA7 (I/O)/TCLKB (input)/
CS3 (input)
PA7 (I/O)/TCLKB (input)/
CS3 (input)
PA6 (I/O)/TCLKA (input)/
CS2 (input)
PA6 (I/O)/TCLKA (input)/
CS2 (input)
PA5 (I/O)/SCK1 (I/O)/
DREQ1 (input)/IRQ1 (input)
PA5 (I/O)/SCK1 (I/O)/
DREQ1 (input)/IRQ1 (input)
PA4 (I/O)/TXD1 (output)
PA4 (I/O)/TXD1 (output)
PA3 (I/O)/RXD1 (input)
PA3 (I/O)/RXD1 (input)
PA2 (I/O)/SCK0 (I/O)/
DREQ0 (input)/IRQ0 (input)
PA2 (I/O)/SCK0 (I/O)/
DREQ0 (input)/IRQ0 (input)
PA1 (I/O)/TXD0 (output)
PA1 (I/O)/TXD0 (output)
PA0 (I/O)/RXD0 (input)
PA0 (I/O)/RXD0 (input)
Note: * SH7016, SH7017 only.
Single Chip Mode*
PA15 (I/O)/CK (output)
PA14 (I/O)
PA13 (I/O)
PA12 (I/O)
PA11 (I/O)
PA10 (I/O)
PA9 (I/O)/TCLKD
(input)/IRQ3 (input)
PA8 (I/O)/TCLKC
(input)/IRQ2 (input)
PA7 (I/O)/TCLKB (input)
PA6 (I/O)/TCLKA (input)
PA5 (I/O)/SCK1 (I/O)/
IRQ1 (input)
PA4 (I/O)/TXD1 (output)
PA3 (I/O)/RXD1 (input)
PA2 (I/O)/SCK0 (I/O)/
IRQ0 (input)
PA1 (I/O)/TXD0 (output)
PA0 (I/O)/RXD0 (input)
17.2.1 Register Configuration
Table 17.2 summarizes the port A register.
Table 17.2 Port A Register
Name
Abbreviation R/W
Port A data register L PADRL
R/W
Initial Value
H'0000
Address
H'FFFF8382
H'FFFF8383
Access Size
8, 16, 32
Rev.5.00 Sep. 27, 2007 Page 476 of 716
REJ09B0398-0500