SH7014 Datasheet, PDF (305/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.58 shows the operation timing when a TGR compare-match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
Counter clear
signal
H'FFFF
H'0000
TGF flag
TCFV flag
Disabled
Figure 10.58 Contention between Overflow and Counter Clearing
Rev.5.00 Sep. 27, 2007 Page 271 of 716
REJ09B0398-0500