SH7014 Datasheet, PDF (23/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6.2.3 On-Chip Peripheral Module Interrupts ................................................................ 77
6.2.4 Interrupt Exception Vectors and Priority Rankings ............................................. 77
6.3 Description of Registers.................................................................................................... 81
6.3.1 Interrupt Priority Registers A to H (IPRA to IPRH) ............................................ 81
6.3.2 Interrupt Control Register (ICR).......................................................................... 82
6.3.3 IRQ Status Register (ISR).................................................................................... 83
6.4 Interrupt Operation............................................................................................................ 85
6.4.1 Interrupt Sequence ............................................................................................... 85
6.4.2 Stack after Interrupt Exception Processing .......................................................... 87
6.5 Interrupt Response Time ................................................................................................... 88
6.6 Data Transfer with Interrupt Request Signals ................................................................... 90
6.6.1 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 90
6.6.2 Treating CPU Interrupt Sources but Not DMAC Activating Sources.................. 90
Section 7 Cache Memory (CAC) .................................................................................... 91
7.1 Overview........................................................................................................................... 91
7.1.1 Features................................................................................................................ 91
7.1.2 Block Diagram ..................................................................................................... 92
7.1.3 Register Configuration......................................................................................... 93
7.2 Register Explanation ......................................................................................................... 94
7.2.1 Cache Control Register (CCR) ............................................................................ 94
7.3 Address Array and Data Array.......................................................................................... 96
7.3.1 Cache Address Array Read/Write Space ............................................................. 96
7.3.2 Cache Data Array Read/Write Space................................................................... 97
7.4 Usage Notes ...................................................................................................................... 98
7.4.1 Cache Initialization .............................................................................................. 98
7.4.2 Forced Access to Address Array and Data Array ................................................ 98
7.4.3 Cache Miss Penalty and Cache Fill Timing ......................................................... 98
7.4.4 Cache Hit after Cache Miss ................................................................................. 100
Section 8 Bus State Controller (BSC) ........................................................................... 101
8.1 Overview........................................................................................................................... 101
8.1.1 Features................................................................................................................ 101
8.1.2 Block Diagram ..................................................................................................... 102
8.1.3 Pin Configuration................................................................................................. 103
8.1.4 Register Configuration......................................................................................... 103
8.1.5 Address Map ........................................................................................................ 104
8.2 Description of Registers.................................................................................................... 107
8.2.1 Bus Control Register 1 (BCR1) ........................................................................... 107
8.2.2 Bus Control Register 2 (BCR2) ........................................................................... 109
Rev.5.00 Sep. 27, 2007 Page xxiii of xxxiv
REJ09B0398-0500