SH7014 Datasheet, PDF (683/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
SCI
Description
Bit
Name
Value
Asynchronous mode
Clock synchronous mode
1, 0 Clock Enable 1 and 0
(CKE1 and CKE0)*⁹
0 0 Internal clock, SCK pin used Internal clock, SCK pin used
for input pin (input signal is for synchronous clock
ignored) or output pin (output output*¹⁰
level is undefined)*¹⁰
0 1 Internal clock, SCK pin used Internal clock, SCK pin used
for clock output*¹¹
for synchronous clock output
1 0 External clock, SCK pin used External clock, SCK pin used
for clock input*¹²
for synchronous clock input
1 1 External clock, SCK pin used External clock, SCK pin used
for clock input*¹²
for synchronous clock input
Notes: 1. The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing
TDRE to 0, or by clearing TIE to 0.
2. RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag (FER, PER,
or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0.
3. The transmit data register empty bit (TDRE) in the serial status register (SSR) is locked at 1.
4. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial status
register (SSR) is cleared to 0 after writing of transmit data into the TDR. Select the transmit format
in the SMR before setting TE to 1.
5. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain
their previous values.
6. Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous
clock input is detected in the clock synchronous mode. Select the receive format in the SMR
before setting RE to 1.
7. The SCI does not transfer receive data from the RSR to the RDR, does not detect receive errors,
and does not set the RDRF, FER, and ORER flags in the serial status register (SSR). When it
receives data that includes MPB = 1, MPB is set to 1, and the SCI automatically clears MPIE to 0,
generates RXI and ERI interrupts (if the TIE and RIE bits in the SCR are set to 1), and allows the
FER and ORER bits to be set.
8. The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR) after it
has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit to 0; or by
clearing the TEIE bit to 0.
9. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the
SCK function for this pin, as well as the I/O direction.
10. Initial value.
11. The output clock frequency is the same as the bit rate.
12. The input clock frequency is 16 times the bit rate.
Rev.5.00 Sep. 27, 2007 Page 649 of 716
REJ09B0398-0500