SH7014 Datasheet, PDF (125/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
Section 7 Cache Memory (CAC)
7.1 Overview
The LSI has an on-chip cache memory (CAC: CAChe) with 1 kbyte of cache data and a 256-entry
cache tag. The cache data and cache tag space can be used as on-chip RAM space when the cache
is not being used.
7.1.1 Features
The CAC has the following features. The cache tag and cache data configuration is shown in
figure 7.1.
• 1-kbyte capacity
• External memory (CS space and DRAM space) instruction code and PC relative data caching
• 256 entry cache tag (tag address 15 bits)
• 4-byte line length
• Direct map replacement algorithm
• Valid flag (1 bit) included for purges
CPU
address
15
8
2
Tag
Entry
address address ^Offset
Valid bit (1 bit)
Cache tag
Tag address (15 bits)
Cache data
Data (32 bits)
256 entries
CMP
Data bus
Hit signal
Figure 7.1 Cache Tag and Cache Data Configuration
Rev.5.00 Sep. 27, 2007 Page 91 of 716
REJ09B0398-0500