SH7014 Datasheet, PDF (243/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Channel 0 (TIOR0L Register)
Bits 7 to 4⎯I/O Control D3 to D0 (IOD3 to IOD0): These bits set the TGR0D register function.
Bit 7 Bit 6 Bit 5 Bit 4
IOD3 IOD2 IOD1 IOD0 Description
0
0
0
0 TGR0D Output disabled
(initial value)
1
is an output _{Initial output is 0}
Output 0 on compare-match
compare
1
0 _register
Output 1 on compare-match
1
Toggle output on compare-match
1
0
0
Output disabled
1
Initial output is 1 Output 0 on compare-match
1
0
Output 1 on compare-match
1
Toggle output on compare-match
1
0
0
0 TGR0D Capture input source Input capture on rising edge
1
is an input is the TIOC0D pin _{Input capture on falling edge}
capture
1
0 _register
Input capture on both edges
1
1
0
0
1
1
0
Capture input source Input capture on TCNT1 count
is channel 1/
up/count down
count clock
1
Note: When the BFB bit of TMDR0 is set to 1 and TGR0D is being used as a buffer register, these
settings become ineffective and input capture/output compares do not occur.
Rev.5.00 Sep. 27, 2007 Page 209 of 716
REJ09B0398-0500