SH7014 Datasheet, PDF (138/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
Table 8.2 Register Configuration
Name
Abbr.
Bus control register 1
BCR1
Bus control register 2
BCR2
Wait state control register 1
WCR1
Wait state control register 2
WCR2
DRAM area control register
DCR
Refresh timer control/status register RTCSR
Refresh timer counter
RTCNT
Refresh time constant register
RTCOR
R/W Initial Value Address Access Size
R/W H'200F
H'FFFF8620 8, 16, 32
R/W H'FFFF
H'FFFF8622 8, 16, 32
R/W H'FFFF
H'FFFF8624 8, 16, 32
R/W H'000F
H'FFFF8626 8, 16, 32
R/W H'0000
H'FFFF862A 8, 16, 32
R/W H'0000
H'FFFF862C 8, 16, 32
R/W H'0000
H'FFFF862E 8, 16, 32
R/W H'0000
H'FFFF8630 8, 16, 32
8.1.5 Address Map
Figure 8.2 shows the address format used by the SH7014.
A31 to A24 A23, A22 A21
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS space when 00000000 (H'00)
DRAM space when 00000001 (H'01)
Reserved (do not access) when 00000010 to 11111110 (H'02 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 8.2 Address Format
This LSI uses 32-bit addresses:
• A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the
corresponding areas when bits A31 to A24 are 00000000.
• A21 to A0 are output externally.
Rev.5.00 Sep. 27, 2007 Page 104 of 716
REJ09B0398-0500