SH7014 Datasheet, PDF (250/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
Bit 3⎯TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when
the TGFD bit of the channel 0 TSR register is set to 1.
This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
Bit 3
TGIED
0
1
Description
Disable interrupt requests (TGID) due to the TGFD bit
Enable interrupt requests (TGID) due to the TGFD bit
(initial value)
Bit 2⎯TGR Interrupt Enable C (TGIEC): Enables or disables TGFC interrupt requests when
the TGFC bit of the Channel 0 TSR register is set to 1.
This bit is reserved for channels 1 and 2. It always reads as 0. The write value should always be 0.
Bit 2
TGIEC
0
1
Description
Disable interrupt requests (TGIC) due to the TGFC bit
Enable interrupt requests (TGIC) due to the TGFC bit
(initial value)
Bit 1⎯TGR Interrupt Enable B (TGIEB): Enables or disables TGFB interrupt requests when
the TGFB bit of the TSR register is set to 1.
Bit 1
TGIEB
0
1
Description
Disable interrupt requests (TGIB) due to the TGFB bit
Enable interrupt requests (TGIB) due to the TGFB bit
(initial value)
Bit 0⎯TGR Interrupt Enable A (TGIEA): Enables or disables TGFA interrupt requests when
the TGFA bit of the TSR register is set to 1.
Bit 0
TGIEA
0
1
Description
Disable interrupt requests (TGIA) due to the TGFA bit
Enable interrupt requests (TGIA) due to the TGFA bit
(initial value)
Rev.5.00 Sep. 27, 2007 Page 216 of 716
REJ09B0398-0500