SH7014 Datasheet, PDF (460/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Compare Match Timer (CMT)
15.3 Operation
15.3.1 Period Count Operation
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 15.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Figure 15.2 Counter Operation
Time
15.3.2 CMCNT Count Timing
One of four clocks (φ/8, φ/32, φ/128, φ/512) obtained by dividing the system clock (CK) can be
selected by the CKS1, CKS0 bits of the CMCSR. Figure 15.3 shows the timing.
CK
Internal clock
CMCNT input
clock
CMCNT
N−1
N
Figure 15.3 Count Timing
N+1
Rev.5.00 Sep. 27, 2007 Page 426 of 716
REJ09B0398-0500