SH7014 Datasheet, PDF (419/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. High Speed A/D Converter ⎯ SH7014 ⎯
When the ADF flag is set to 1, if the ADIE bit is also set to 1, an ADI interrupt is issued. After the
ADCSR is read, the ADF flag is cleared by a 0 write.
With select single mode, the high speed A/D converter goes into standby mode at the end of every
conversion cycle. The high speed A/D converter is restarted by software, or a timer trigger. When
the number of conversion cycles shown in table 13.4 have ended, the ADF flag is set to 1.
Table 13.4 Conversion Channel and ADF Flag Setting/Clearing Conditions During Buffer
Operation 1
Channel Setting
CH2 CH1 CH0 BUFE1, BUFE0 = B'01
000
AN0 1 time (ADDRA)
1
10
AN0 2 times (ADDRB)
*
1
*
1 ⎯⎯ *
Note: * See table 13.5.
Sampling Channel
BUFE1, BUFE0 = B'10 BUFE1, BUFE0 = B'11
AN0, AN1 1 time
(ADDRB)
AN0 1 time (ADDRA)
AN0 2 times (ADDRB)
AN0, AN1 2 times
(ADDRD)
AN0 3 times (ADDRC)
AN0 4 times (ADDRD)
*
*
Combined Group Mode and Buffer Operation: Continuous conversion is possible on analog
input channels (AN0 and AN1) specified by bits BUFE1 and BUFE0 as well as AN4 to AN7 due
to setting of bits CH2 to CH0.
Table 13.5 shows conversion during buffer operation and ADF flag setting conditions. The ADF
flag is set at the point in the table when the final conversion has ended. In this case, conversion is
performed on the analog input corresponding with the ADDR specified in the buffer register. For
example, when BUFE1 and BUFE0 = B'11 and CH2 to CH0 = B'110, conversion results are stored
in ADDRA and ADDRE to ADDRG. Also, contents of ADDRA to ADDRC before the start of
conversion are transferred to ADDRB to ADDRD.
In single mode, conversion is halted after the ADF flag has been set to 1. Conversion continues in
scan mode.
Rev.5.00 Sep. 27, 2007 Page 385 of 716
REJ09B0398-0500