SH7014 Datasheet, PDF (746/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix C Pin States
Table C.5 Pin Settings for DRAM Space
DRAM Space
16-Bit Space
Pin Name
8-Bit Space Upper Word
Lower Word
Word/Longword
CS0 to CS3
RAS*¹
CASH*²
CASL*²
H
Valid
H
Valid
H
Valid
Valid
H
H
Valid
H
Valid
H
Valid
Valid
Valid
RDWR
R
H
H
H
H
WL
L
L
L
AH
L
L
L
L
RD
RL
L
L
L
WH
H
H
H
WRH
RH
H
H
H
WH
L
H
L
WRL
RH
H
H
H
WL
H
L
L
A21 to A0
Address
Address
Address
Address
D15 to D8
Hi-Z
Data
Hi-Z
Data
D7 to D0
Data
Hi-Z
Data
Data
Legend:
R: Read
W: Write
Valid: Asserted (low) at a timing determined by the DRAM access strobe waveform
Notes: 1. L asserted in RAS down mode or refresh mode.
2. L asserted in refresh mode.
Rev.5.00 Sep. 27, 2007 Page 712 of 716
REJ09B0398-0500