SH7014 Datasheet, PDF (300/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Multifunction Timer Pulse Unit (MTU)
10.7.6 Contention between TGR Read and Input Capture
If an input capture signal is issued in the T₁ state of the TGR read cycle, the read data is that after
input capture transfer (figure 10.53).
TGR read cycle
T₁
T₂
φ
Address
Read signal
Input capture
signal
TGR
TGR
address
X
M
Internal data
M
bus
Figure 10.53 TGR Read and Input Capture Contention
Rev.5.00 Sep. 27, 2007 Page 266 of 716
REJ09B0398-0500