SH7014 Datasheet, PDF (11/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
10.4.4 Buffer Operation 237
Buffer Operation
Examples⎯when TGR
Is an Input Capture
Register
Figure 10.20 Buffer 238
Operation Example
(Input Capture Register)
10.4.6 PWM Mode 240
10.4.7 Phase Counting 250
Mode
Phase Counting Mode
Application Example:
10.6.1 Input/Output 254
Timing
Output Compare Output
Timing:
10.7.10 TCNT2 Write 269
and Overflow/Underflow
Contention in Cascade
Connection
Revision (See Manual for Details)
Description amended
Figure 10.20 shows an example of TGRA set as an input
capture register with the TGRA and TGRC registers set for
buffer operation.
Figure amended
TIOC0A
Description amended
A period can be set for a register by using the TGR compare-
match as a counter clear source. All channels can be
independently set to PWM mode. Synchronous operation is
also possible.
Description amended
The channel 1 TGR1A and TGR1B registers are set for the
input capture function, the channel 0 TGR0A and TGR0C
register compare-match is used as an input capture source,
and all of the control period increment and decrement values
are stored. This procedure enables the accurate detection of
position and speed.
Description amended
The compare-match signal is generated at the final state of
TCNT and TGR matching. When a compare-match signal is
issued, the output value set in TIOR is output to the output
compare output pin (the TIOC pin). After TCNT and TGR
matching, a compare-match signal is not issued until
immediately before the TCNT input clock.
Description amended
With timer counters TCNT1 and TCNT2 in a cascade
connection, when a contention occurs during TCNT1 count
(during a TCNT2 overflow/underflow) in the T₂ state of the
TCNT2 write cycle, the write to TCNT2 is conducted, and the
TCNT1 count signal is prohibited. At this point, if there is match
with TGR1A and the TCNT1 value, a compare signal is
issued. Furthermore, when the TCNT1 count clock is selected
as the input capture source of channel 0, TGRA0 to TGRD0
carry out the input capture operation. In addition, when the
compare match/input capture is selected as the input capture
source of TGRB1, TGRB1 carries out input capture operation.
The timing is shown in figure 10.57.
Rev.5.00 Sep. 27, 2007 Page xi of xxxiv
REJ09B0398-0500