SH7014 Datasheet, PDF (143/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.2.2 Bus Control Register 2 (BCR2)
BCR2 is a 16-bit read/write register that specifies the number of idle cycles and CS signal assert
extension of each CS space.
BCR2 is initialized by power-on resets to H'FFFF, but is not initialized by software standbys.
Bit:
Initial value:
R/W:
15
IW31
1
R/W
14
IW30
1
R/W
13
IW21
1
R/W
12
IW20
1
R/W
11
IW11
1
R/W
10
IW10
1
R/W
9
IW01
1
R/W
8
IW00
1
R/W
Bit:
Initial value:
R/W:
7
CW3
1
R/W
6
CW2
1
R/W
5
CW1
1
R/W
4
CW0
1
R/W
3
SW3
1
R/W
2
SW2
1
R/W
1
SW1
1
R/W
0
SW0
1
R/W
Bits 15 to 8⎯Idles between Cycles (IW31, IW30, IW21, IW20, IW11, IW10, IW01, IW00):
These bits specify idle cycles inserted between consecutive accesses when the second one is to a
different CS area after a read. Idles are used to prevent data conflict between ROM (and other
memories, which are slow to turn the read data buffer off), fast memories, and I/O interfaces. Even
when access is to the same area, idle cycles must be inserted when a read access is followed
immediately by a write access. The idle cycles to be inserted comply with the area specification of
the previous access. Refer to section 8.6, Waits between Access Cycles, for details.
IW31, IW30 specify the idle between cycles for CS3 space; IW21, IW20 specify the idle between
cycles for CS2 space; IW11, IW10 specify the idle between cycles for CS1 space and IW01, IW00
specify the idle between cycles for CS0 space.
Bit 15
IW31
0
1
Bit 14
IW30
0
1
0
1
Description
No idle cycle after accessing CS3 space
Inserts one idle cycle
Inserts two idle cycles
Inserts three idle cycles
(initial value)
Rev.5.00 Sep. 27, 2007 Page 109 of 716
REJ09B0398-0500