SH7014 Datasheet, PDF (8/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
1.3.1 Pin Arrangement 9
Figure 1.4 SH7016,
SH7017 Pin
Arrangement (FP-112
Top View)
5.3.1 Address Error 64
Sources
Table 5.5 Bus Cycles
and Address Errors
5.4.1 Interrupt Sources 65
6.3.1 Interrupt Priority 82
Registers A to H (IPRA
to IPRH)
8.1.3 Pin Configuration 103
Table 8.1 Pin
Configuration
8.1.5 Address Map 105
Table 8.3 Address Map
• In on-chip ROM
enabled mode
8.2.1 Bus Control
108
Register 1 (BCR1)
Bit 0⎯CS0 Space Size
Specification (A0SZ)
Revision (See Manual for Details)
Note amended
Note: * V_CC in the SH7016, FWP in the SH7017 (except
FWE pin in the programmer mode).
Title added and table amended
Bus Cycle
Type
Bus
Master Bus Cycle Description
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from other than on-chip peripheral
module space*
Instruction fetched from on-chip peripheral module
space*
Instruction fetched from external memory space when
in single chip mode
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
Address error occurs
Title added and description amended
Table 5.6 shows the sources that start up interrupt exception
processing. These are divided into NMI, IRQ and on-chip
peripheral modules.
Description amended
IPRA to IPRH are initialized to H'0000 by a power-on reset .
They are not initialized in standby mode.
Table amended
Signal
WRH
WRL
I/O
O
O
Description
Strobe that indicates a write cycle to the higher byte (D15 to D8) for
ordinary space/multiplex I/O. Also output during DRAM access.
Strobe that indicates a write cycle to the lower byte (D7 to D0) for ordinary
space/multiplex I/O. Also output during DRAM access.
Table amdended
Addresss
H'00000000 to H'0001FFF*⁴
Note added
Note: A0SZ is effective only in on-chip ROM effective mode.
In on-chip ROM ineffective mode, the CS0 space bus
size is specified by the mode pin.
Rev.5.00 Sep. 27, 2007 Page viii of xxxiv
REJ09B0398-0500