SH7014 Datasheet, PDF (553/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. 128 kB Flash Memory (F-ZTAT)
Start
*1
Set SWE bit in FLMCR1
Wait 10 μs
n=1
Set EBR1
*3
WDT Enable
Set ESU-bit of FLMCR1
Wait 200 μs
Set E-bit of FLMCR1
Wait 5 ms
Clear E-bit of FLMCR1
Wait 10 μs
Clear ESU-bit of FLMCR1
Wait 10 μs
WDT Disable
Set EV-bit of FLMCR1
Wait 20 μs
Erase start
Erase stop
Set top block address to verify address
n←n+1
Dummy write H'FF to verify address
Wait 2 μs
Address
increment
NG
Read verify data
Verify data = all "1"?
OK
Last block address?
OK
Clear EV-bit of FLMCR1
*2
NG
Wait 5 μs
Clear EV-bit of FLMCR1
Wait 5 μs
NG
*4
All
objective blocks
erased?
OK
Clear SWE-bit in FLMCR1
NG
n > 60
OK
Clear SWE-bit of FLMCR1
Erase complete
Erase error
Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 18.14 Erase/Erase-Verify Flowchart (Single-Block Erase)
Rev.5.00 Sep. 27, 2007 Page 519 of 716
REJ09B0398-0500