SH7014 Datasheet, PDF (130/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
7.3 Address Array and Data Array
There is a special cache space for controlling the cache. This space is divided into an address array
and a data array, where addresses (tag address, including valid bit) and data (4-byte line length) for
cache control are recorded. The special cache space is shown in table 7.2. It can be used as on-chip
RAM space when the cache is not being used.
Table 7.2 Special Cache Space
Space Classification
Address array
Data array
Address
H'FFFFF000 to H'FFFFF3FF
H'FFFFF400 to H'FFFFF7FF
Size
1 kbyte
1 kbyte
Bus Width
32 bits
32 bits
7.3.1 Cache Address Array Read/Write Space
The cache address array has a compulsory read/write (figure 7.3).
31
10 9
Upper 22 bits of the address array space address
Address
(22 bits)
21 0
Entry address
⎯
(8 bits)
(2 bits)
31
26 25 24
Data
⎯
(6 bits)
Tag address
(15 bits)
10 9
0
⎯
(10 bits)
Valid bit (1 bit)
Figure 7.3 Cache Address Array
Address Array Read: Designates entry address and reads out the corresponding tag address
value/valid bit value.
Address Array Write: Designates entry address and writes the designated tag address value/valid
bit value.
Rev.5.00 Sep. 27, 2007 Page 96 of 716
REJ09B0398-0500