SH7014 Datasheet, PDF (18/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
18.5.4 RAM Emulation 503
Register (RAMER)
18.7.2 Program-Verify 512
Mode
Figure 18.13 Program/
Program-Verify
Flowchart
Revision (See Manual for Details)
Description amended
RAMER specifies the area of flash memory to be overlapped
with part of RAM when emulating real-time flash memory
programming. RAMER is initialized to H'0000 by a reset and in
hardware standby mode. It is not initialized in software standby
mode. RAMER settings should be made in user mode or user
program mode.
Figure amended and note 5 added
Start
Set SWE-bit of FLMCR1
Wait 10 μs
*5
Store 32 bytes write data in write
*4
data area and rewrite data area
n=1
m=0
Successively write 32-byte data in rewrite data _*1
area in RAM to flash memory
Enable WDT
Set PSU bit in FLMCR1(2)
Wait 50 μs
Set PSU bit in FLMCR1(2)
Wait 200 μs
Set PSU bit in FLMCR1(2)
Wait 10 μs
Set PSU bit in FLMCR1(2)
*5
Write start
*5
Write end
*5
Wait 10 μs
*5
Disable WDT
Set PSU bit in FLMCR1(2)
Wait 4 μs
*5
Increment address
Perform dummy-write of H'FF to verify address
Wait 2 μs
*5
Read verify data
*2
*3
Write data = Verify data?
OK
NG
m=1
Operate rewrite data
*3
Transfer rewrite data to rewrite data area ^*4
n←n+1
32 byte data
NG
verify complete?
OK
Set PSU bit in FLMCR1(2)
Wait 4 μs
m = 0?
OK
Clear SWE bit of FLMCR1
Write end
*5
NG
n ≥ 1000?
*5 _NG
OK
Clear SWE bit of FLMCR1
Write failure
Note: 5. Set the values of x, y, z, α, β, γ, ε, η, and N to match
the characteristics of the memory device.
Rev.5.00 Sep. 27, 2007 Page xviii of xxxiv
REJ09B0398-0500