SH7014 Datasheet, PDF (464/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Compare Match Timer (CMT)
15.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T₂ state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 15.7 shows the timing.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNT
Internal
write signal
CMCNT
input clock
CMCNT
N
M
CMCNT write data
Figure 15.7 CMCNT Word Write and Increment Contention
Rev.5.00 Sep. 27, 2007 Page 430 of 716
REJ09B0398-0500