SH7014 Datasheet, PDF (581/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Mask ROM
19. Mask ROM
19.1 Overview
This LSI is available with 64 kbytes or 128 kbytes of on-chip ROM. The on-chip ROM is
connected to the CPU, direct memory access controller (DMAC) through a 32-bit data bus (figures
19.1 and 19.2). The CPU and DMAC can access the on-chip ROM in 8, 16 and 32-bit widths.
Data in the on-chip ROM can always be accessed in one cycle.
Internal data bus (32-bit)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0000FFFC
H'0000FFFD
H'0000FFFE
H'0000FFFF
Figure 19.1 Mask ROM Block Diagram (64 kbyte version)
Rev.5.00 Sep. 27, 2007 Page 547 of 716
REJ09B0398-0500