SH7014 Datasheet, PDF (162/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.4.2 Basic Timing
This LSI supports 2 CAS format DRAM access. The DRAM access basic timing is a minimum of
3 cycles for normal mode. Figure 8.7 shows the basic DRAM access timing. DRAM space access
is controlled by RAS, CASx and RDWR signals. The following signals are associated with
transfer of these actual byte locations: CASH (bits 15 to 8) and CASL (bits 7 to 0). However, the
signals for ordinary space, WRx and RD, are also output during the DMAC single transfer column
address cycle period. T_p is the precharge cycle, T_r is the RAS assert cycle, T_c is the CAS assert
cycle and T_c2 is the read data fetch cycle.
T_p
T_r
T_c1
T_c2
CK
Address
Row
Column
Data
Write
RAS
CASx
RDWR
Read
Data
RAS
CASx
RDWR
Figure 8.7 DRAM Bus Cycle (Normal Mode, TPC = 0, RCD = 0, No Waits)
Rev.5.00 Sep. 27, 2007 Page 128 of 716
REJ09B0398-0500