SH7014 Datasheet, PDF (134/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Cache Memory (CAC)
CK
Internal
address
Address
RAS
CASx
Data
Miss-hit
Idle cycle
ROW
Idle cycle
COLUMN
RAS assert extension
Idle cycle
Figure 7.7 Cache Fill Timing in Case of Non-Consecutive Cache Miss from DRAM Space
(Normal Mode, TPC = 0, RCD = 0, No Wait)
DRAM access
CS space
access
DRAM access
CK
Internal
address
Address
RAS
CASx
Miss-hit
ROW
COLUMN
Wait
Miss-hit
CS space
COLUMN
RAS assert extension
Data
Figure 7.8 Cache Fill Timing in Case of Consecutive Cache Misses from DRAM Space
(RAS Down Mode, TPC = 0, RCD = 0, No Wait)
7.4.4 Cache Hit after Cache Miss
The first cache hit after a cache miss is regarded as a cache miss, and a cache fill without idle
cycle generation is performed. The next hit operates as a cache hit.
Rev.5.00 Sep. 27, 2007 Page 100 of 716
REJ09B0398-0500