SH7014 Datasheet, PDF (136/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Bus State Controller (BSC)
8.1.2 Block Diagram
Figure 8.1 shows the BSC block diagram.
WAIT
CS0 to CS3
AH
RD
RDWR
WRH, WRL
CASH, CASL
RAS
CMI interrupt request
Wait
control
unit
Area
control
unit
Memory
control
unit
Bus
interface
WCR1
WCR2
BCR1
BCR2
DCR
RTCSR
RTCNT
Comparator
Interrupt
controller
Legend:
WCR1: Wait control register 1
WCR2: Wait control register 2
BCR1: Bus control register 1
BCR2: Bus control register 2
RTCOR
BSC
DCR: DRAM area control register
RTCNT: Refresh timer counter
RTCOR: Refresh timer constant register
RTCSR: Refresh timer control/status register
Figure 8.1 BSC Block Diagram
Rev.5.00 Sep. 27, 2007 Page 102 of 716
REJ09B0398-0500