SH7014 Datasheet, PDF (342/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

12. Serial Communication Interface (SCI)
12.2 Register Descriptions
12.2.1 Receive Shift Register (RSR)
Bit: 7
6
5
4
3
2
1
0
R/W: ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
The receive shift register (RSR) receives serial data. Data input at the RxD pin is loaded into the
RSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte
has been received, it is automatically transferred to the RDR.
The CPU cannot read or write the RSR directly.
12.2.2 Receive Data Register (RDR)
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
The receive data register (RDR) stores serial receive data. The SCI completes the reception of one
byte of serial data by moving the received data from the receive shift register (RSR) into the RDR
for storage. The RSR is then ready to receive the next data. This double buffering allows the SCI
to receive data continuously.
The CPU can read but not write the RDR. The RDR is initialized to H'00 by a power-on reset or in
standby mode.
12.2.3 Transmit Shift Register (TSR)
Bit: 7
6
5
4
3
2
1
0
R/W: ⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB
(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data
Rev.5.00 Sep. 27, 2007 Page 308 of 716
REJ09B0398-0500