SH7014 Datasheet, PDF (519/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. I/O Ports (I/O)
17.6.2 Port E Data Register (PEDR)
Bit: 15
14
13
12
11
10
9
8
PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
PEDR is a 16-bit read/write register that stores data for port E. The bits PE15DR to PE0DR
correspond to the PE15/DACK1 to PE0/TIOC0A/DREQ0 pins. When the pins are used as
ordinary outputs, they will output whatever value is written in the PEDR; when PEDR is read, the
register value will be read regardless of the pin status. When the pins are used as ordinary inputs,
the pin status rather than the register value is read directly when PEDR is read. When a value is
written to PEDR, that value can be written into PEDR, but it will not affect the pin status. Table
17.15 shows the read/write operations of the port E data register.
PEDR is initialized by a external power-on reset. However, PEDR is not initialized for a reset by
WDT, standby mode, or sleep mode, so the previous data is retained.
Table 17.15 Read/Write Operation of the Port E Data Register (PEDR)
PEIOR
0
1
Pin Status
Read
Ordinary input Pin status
Other function Pin status
Ordinary output PEDR value
Other function PEDR value
Write
Can write to PEDR, but it has no effect on pin status
Can write to PEDR, but it has no effect on pin status
Value written is output by pin
Can write to PEDR, but it has no effect on pin status
Rev.5.00 Sep. 27, 2007 Page 485 of 716
REJ09B0398-0500