SH7014 Datasheet, PDF (117/754 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Interrupt Controller (INTC)
Bit 8⎯NMI Edge Select (NMIE)
Bit 8
NMIE
0
1
Description
Interrupt request is detected on falling edge of NMI input (initial value)
Interrupt request is detected on rising edge of NMI input
Bits 7 to 4, 1, 0⎯IRQ0 to IRQ3, IRQ6, IRQ7 Sense Select (IRQ0S to IRQ3S, IRQ6S,
IRQ7S): These bits set the IRQ0 to IRQ3, IRQ6, IRQ7 interrupt request detection mode.
Bits 7 to 4, 1, 0
IRQ0S to IRQ3S, IRQ6S,
IRQ7S
Description
0
Interrupt request is detected on low level of IRQ input (initial value)
1
Interrupt request is detected on falling edge of IRQ input
6.3.3 IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input
pins IRQ0 to IRQ3, IRQ6, IRQ7. When IRQ interrupts are set to edge detection, held interrupt
requests can be withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1.
A power-on reset initializes ISR but the standby mode does not.
Bit: 15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
IRQ0F IRQ1F IRQ2F IRQ3F ⎯
Initial value: 0
0
0
0
0
R/W: R/W R/W R/W R/W
R
2
1
0
⎯ IRQ6F IRQ7F
0
0
0
R
R/W R/W
Bits 15 to 8, 3, 2⎯Reserved: These bits always read as 0. The write value should always be 0.
Rev.5.00 Sep. 27, 2007 Page 83 of 716
REJ09B0398-0500