HD64F3048VTF8 Datasheet, PDF (97/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 2 CPU
T₁
T₂
T₃
φ
Address bus
Address
AS, RD, HWR, LWR
D₁₅ to D₀
High
High-impedance
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
Rev. 3.00 Sep 27, 2006 page 69 of 872
REJ09B0325-0300