HD64F3048VTF8 Datasheet, PDF (194/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
7.2.2 Refresh Timer Control/Status Register (RTMCSR)
RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also
enables or disables interrupt requests when the refresh controller is used as an interval timer.
Bit
7
6
5
4
3
2
1
0
CMF CMIE CKS2 CKS1 CKS0



Initial value
0
0
0
0
0
1
1
1
Read/Write R/(W)* R/W R/W R/W R/W



Clock select 2 to 0
These bits select an
internal clock source
for input to RTCNT
Reserved bits
Compare match interrupt enable
Enables or disables the CMI interrupt requested by CMF
Compare match flag
Status flag indicating that RTCNT has matched RTCOR
Note: * Only 0 can be written, to clear the flag.
Bits 7 and 6 are initialized by a reset and in standby mode. Bits 5 to 3 are initialized by a reset and
in hardware standby mode, but retain their previous values on transition to software standby mode.
Bit 7—Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR
values have matched.
Bit 7: CMF
0
1
Description
[Clearing condition]
Cleared by reading CMF when CMF = 1, then writing 0 in CMF
[Setting condition]
When RTCNT = RTCOR
Rev. 3.00 Sep 27, 2006 page 166 of 872
REJ09B0325-0300