HD64F3048VTF8 Datasheet, PDF (79/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 2 CPU
Table 2.10 Block Transfer Instruction
Instruction
EEPMOV.B
Size
—
EEPMOV.W —
Function
if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Transfers a data block according to parameters set in general
registers R4L or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5:
Starting source address
ER6:
Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
Rev. 3.00 Sep 27, 2006 page 51 of 872
REJ09B0325-0300