HD64F3048VTF8 Datasheet, PDF (407/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Examples of Complementary PWM Mode
Figure 10.35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4
operate as up/down-counters, counting down from compare match between TCNT3 and GRA3
and counting up from the point at which TCNT4 underflows. During each up-and-down counting
cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4,
and GRB4. Since TCNT3 is initially set to a higher value than TCNT4, compare match events
occur in the sequence TCNT3, TCNT4, TCNT4, TCNT3.
TCNT3 and
TCNT4 values
GRA3
GRB3
GRA4
GRB4
H'0000
TIOCA₃
Down-counting starts at compare
match between TCNT3 and GRA3
TCNT3
TCNT4
Up-counting starts when
TCNT4 underflows
Time
TIOCB₃
TIOCA₄
TOCXA₄
TIOCB₄
TOCXB₄
Figure 10.35 Operation in Complementary PWM Mode (Example 1, OLS3 = OLS4 = 1)
Rev. 3.00 Sep 27, 2006 page 379 of 872
REJ09B0325-0300