HD64F3048VTF8 Datasheet, PDF (317/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 9 I/O Ports
Port 8 Data Register (P8DR)
P8DR is an 8-bit readable/writable register that stores output data for pins P8₄ to P8₀. While port 8
acts as an output port, the value of this register is output. When a bit in P8DDR is set to 1, if port 8
is read the value of the corresponding P8DR bit is returned. When a bit in P8DDR is cleared to 0,
if port 8 is read the corresponding pin level is read.
Bits 7 to 5 are reserved. They cannot be modified and always are read as 1.
Bit
7
6
5
4
3
2
1
0



P8 ₄
P8 ₃
P8 ₂
P8 ₁
P8 ₀
Initial value
1
1
1
0
0
0
0
0
Read/Write



R/W
R/W
R/W
R/W
R/W
Reserved bits
Port 8 data 4 to 0
These bits store data
for port 8 pins
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 3.00 Sep 27, 2006 page 289 of 872
REJ09B0325-0300