HD64F3048VTF8 Datasheet, PDF (431/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between General Register Write and Compare Match
If a compare match occurs in the T₃ state of a general register write cycle, writing takes priority
and the compare match signal is inhibited. See figure 10.64.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
TCNT
N
N+1
GR
Compare match signal
N
M
General register write data
Inhibited
Figure 10.64 Contention between General Register Write and Compare Match
Rev. 3.00 Sep 27, 2006 page 403 of 872
REJ09B0325-0300