HD64F3048VTF8 Datasheet, PDF (295/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 9 I/O Ports
9.3.2 Register Descriptions
Table 9.3 summarizes the registers of port 2.
Table 9.3 Port 2 Registers
Address^* Name
Abbreviation R/W
H'FFC1
Port 2 data direction
P2DDR
W
register
H'FFC3
Port 2 data register
P2DR
R/W
H'FFD8
Port 2 input pull-up MOS P2PCR
R/W
control register
Note: * Lower 16 bits of the address.
Initial Value
Modes 1 to 4 Modes 5 to 7
H'FF
H'00
H'00
H'00
H'00
H'00
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2.
Bit
7
6
5
4
3
2
1
0
P2₇DDR P2₆DDR P2₅DDR P2₄DDR P2₃DDR P2₂DDR P2₁DDR P2₀DDR
Modes ^{Initial value 1}
1
1
1
1
1
1
1
1 to 4 _{Read/Write }







Modes ^{Initial value 0}
0
0
0
0
0
0
0
5 to 7 _{Read/Write W}
W
W
W
W
W
W
W
Port 2 data direction 7 to 0
These bits select input or
output for port 2 pins
Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P2DDR values are fixed at 1
and cannot be modified. Port 2 functions as an address bus.
Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 2 is
an input port. A pin in port 2 becomes an address output pin if the corresponding P2DDR bit is set
to 1, and a generic input port if this bit is cleared to 0.
Mode 7 (Single-Chip Mode): Port 2 functions as an input/output port. A pin in port 2 becomes an
output port if the corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0.
In modes 1 to 4, P2DDR always returns 1 when read. No value can be written to.
Rev. 3.00 Sep 27, 2006 page 267 of 872
REJ09B0325-0300