HD64F3048VTF8 Datasheet, PDF (316/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 9 I/O Ports
Port 8 Data Direction Register (P8DDR)
P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
Bits 7 to 5 are reserved. They cannot be modified and are always read as 1.
Bit
7
6
5
4
3
2
1
0


 P8₄DDR P8₃DDR P8₂DDR P8₁DDR P8₀DDR
Modes ^{Initial value 1}
1
1
1
0
0
0
0
1 to 4 _{Read/Write }


W
W
W
W
W
Modes ^{Initial value 1}
1
1
0
0
0
0
0
5 to 7 _{Read/Write }


W
W
W
W
W
Reserved bits
Port 8 data direction 4 to 0
These bits select input or
output for port 8 pins
Modes 1 to 6 (Expanded Modes): When bits in P8DDR bit are set to 1, P8₄ to P8₁ become CS₀ to
CS₃ output pins. When bits in P8DDR are cleared to 0, the corresponding pins become input ports.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), following a reset only CS₀ is
output. The other three pins are input ports. In modes 5 and 6 (expanded modes with on-chip
ROM enabled), following a reset all four pins are input ports.
When the refresh controller is enabled, P8₀ is used unconditionally for RFSH output. When the
refresh controller is disabled, P8₀ becomes a generic input/output port according to the P8DDR
setting. For details see table 9.15.
Mode 7 (Single-Chip Mode): Port 8 is a generic input/output port. A pin in port 8 becomes an
output port if the corresponding P8DDR bit is set to 1, and an input port if this bit is cleared to 0.
P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read.
P8DDR is initialized to H'F0 in modes 1 to 4 and H'E0 in modes 5 to 7 by a reset and in hardware
standby mode. In software standby mode it retains its previous setting, so if a P8DDR bit is set to
1 while port 8 acts as an I/O port, the corresponding pin maintains its output state in software
standby mode.
Rev. 3.00 Sep 27, 2006 page 288 of 872
REJ09B0325-0300