HD64F3048VTF8 Datasheet, PDF (411/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

GRA3
GR
Section 10 16-Bit Integrated Timer Unit (ITU)
H'0000
BR
Not allowed
GR
Figure 10.39 Changing a General Register Setting by Buffer Transfer (Example 1)
 Buffer transfer at transition from up-counting to down-counting
If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a
buffer register value outside this range. Conversely, if the general register value is outside
this range, do not transfer a value within this range. See figure 10.40.
GRA3 + 1
GRA3
Illegal changes
GRA3 − T + 1
GRA3 − T
TCNT3
TCNT4
Figure 10.40 Changing a General Register Setting by Buffer Transfer (Caution 1)
 Buffer transfer at transition from down-counting to up-counting
If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer
register value outside this range. Conversely, when a general register value is outside this
range, do not transfer a value within this range. See figure 10.41.
Rev. 3.00 Sep 27, 2006 page 383 of 872
REJ09B0325-0300