HD64F3048VTF8 Datasheet, PDF (52/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 1 Overview
Item
Models with Dual Power Supply:
H8/3048F^*1
Models with Single Power Supply:
H8/3048F-ONE
Division of RAM
emulation block
On-chip RAM
H'EF10
H'F000
H'F1FF
H'FF0F
Flash memory
H'00000
On-chip RAM
H'EF10
H'F000
H'1EFFF
H'1F000
H'1F200
H'1F400
H'1F600
H'1F800
H'1FA00
H'1FC00
H'1FE00
H'1FFFF
H'F3FF
H'FF0F
Flash memory
H'00000
H'00400
H'00800
H'00C00
H'01000
H'1FFFF
Reset during
operation
A/D ADCR
The RES signal must be kept low during The RES signal must be kept low during
at least 6 system clock (6φ) cycles.
at least 20 system clock (20φ) cycles.
(RES pulse width t_RESW = min. 6.0 t_cyc)
(RES pulse width t_RESW = min. 20 t_cyc)
ADCR (H'FFE9)
ADCR (H'FFE9)
Initial value: H'7F
Initial value: H'7E
Only bit 7 can be read or written.
Only bit 7 can be read or written.
Other bits are reserved and always read Bit 0 is reserved and must not be set to
as 1; writing to these bits is invalid.
1.
Other bits are reserved and always read
as 1; writing to these bits is invalid.
WDT RSTCSR
RSTCSR (H'FFAB)
RSTCSR (H'FFAB)
Initial value: H'3F
Initial value: H'3F
Only bits 7 and 6 can be read or written. Only bit 7 can be read or written.
Other bits are reserved and always read Bit 6 is reserved and must not be set to
as 1; writing to these bits is invalid.
1.
Other bits are reserved and always read
as 1; writing to these bits is invalid.
Rev. 3.00 Sep 27, 2006 page 24 of 872
REJ09B0325-0300