HD64F3048VTF8 Datasheet, PDF (548/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 14 Smart Card Interface
Bits 7 to 5: These bits operate as in normal serial communication. For details see section 13,
Serial Communication Interface.
Bit 4—Error Signal Status (ERS): In smart card interface mode, this flag indicates the status of
the error signal sent from the receiving device to the transmitting device. The smart card interface
does not detect framing errors.
Bit 4: ERS
Description
0
Indicates normal data transmission, with no error signal returned (Initial value)
[Clearing conditions]
The chip is reset or enters standby mode.
Software reads ERS while it is set to 1, then writes 0.
1
Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
A low error signal was sampled.
Note: Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
value.
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 13,
Serial Communication Interface. The setting conditions for transmit end (TEND, bit 2), however,
are modified as follows.
Bit 2: TEND
Description
0
Transmission is in progress
[Clearing conditions]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
The DMAC writes data in TDR.
1
End of transmission
(Initial value)
[Setting conditions]
The chip is reset or enters standby mode.
The TE bit and FER/ERS bit are both cleared to 0 in SCR.
TDRE is 1 and FER/ERS is 0 at a time 2.5 etu after the last bit of a 1-byte
serial character is transmitted (normal transmission)
Note: An etu (elementary time unit) is the time needed to transmit one bit.
Rev. 3.00 Sep 27, 2006 page 520 of 872
REJ09B0325-0300