HD64F3048VTF8 Datasheet, PDF (519/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 13 Serial Communication Interface
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
2. Receive data is stored in RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving, the SCI makes the following checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
is checked.
c. Status check: The RDRF flag must be 0 so that receive data can be transferred from RSR
into RDR.
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one
of the checks fails (receive error)*, the SCI operates as indicated in table 13.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
is not set to 1. Be sure to clear the error flags to 0.
4. When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 13.11 Receive Error Conditions
Receive Error
Overrun error
Framing error
Abbreviation
ORER
FER
Condition
Receiving of next data ends
while RDRF flag is still set
to 1 in SSR
Stop bit is 0
Parity error
PER
Parity of receive data differs
from even/odd parity setting
in SMR
Data Transfer
Receive data not transferred
from RSR to RDR
Receive data transferred from
RSR to RDR
Receive data transferred from
RSR to RDR
Rev. 3.00 Sep 27, 2006 page 491 of 872
REJ09B0325-0300