HD64F3048VTF8 Datasheet, PDF (248/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 8 DMA Controller
8.4 Operation
8.4.1 Overview
Table 8.5 summarizes the DMAC modes.
Table 8.5 DMAC Modes
Transfer Mode
Short address
mode
Full address
mode
I/O mode
Idle mode
Repeat mode
Normal mode
Block transfer
mode
Activation
Notes
Compare match/input
capture A interrupt from
ITU channels 0 to 3
Transmit-data-empty and
receive-data-full interrupts
from SCI channel 0
• Up to four channels can
operate independently
• Only the B channels
support external requests
External request
Auto-request
•
External request
Compare match/input
capture A interrupt from ITU •
channels 0 to 3
External request
A and B channels are
paired; up to two channels
are available
Burst mode or cycle-steal
mode can be selected for
auto-requests
A summary of operations in these modes follows.
I/O Mode
One byte or word is transferred per request. A designated number of these transfers are executed.
A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit
address and one 8-bit address are specified. The transfer direction is determined automatically
from the activation source.
Idle Mode
One byte or word is transferred per request. A designated number of these transfers are executed.
A CPU interrupt can be requested at completion of the designated number of transfers. One 24-bit
address and one 8-bit address are specified. The addresses are held fixed. The transfer direction is
determined automatically from the activation source.
Rev. 3.00 Sep 27, 2006 page 220 of 872
REJ09B0325-0300