HD64F3048VTF8 Datasheet, PDF (305/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 9 I/O Ports
9.6.2 Register Descriptions
Table 9.8 summarizes the registers of port 5.
Table 9.8 Port 5 Registers
Address^* Name
Abbreviation R/W
H'FFC8
Port 5 data direction
P5DDR
W
register
H'FFCA
Port 5 data register
P5DR
R/W
H'FFDB
Port 5 input pull-up MOS P5PCR
R/W
control register
Note: * Lower 16 bits of the address.
Initial Value
Modes 1 to 4 Modes 5 to 7
H'FF
H'F0
H'F0
H'F0
H'F0
H'F0
Port 5 Data Direction Register (P5DDR)
P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5.
Bits 7 to 4 are reserved. They cannot be modified and are always read as 1.
Bit
7
6
5
4
3
2
1
0



 P5₃DDR P5₂DDR P5₁DDR P5₀DDR
Modes ^{Initial value 1}
1
1
1
1
1
1
1
1 to 4 _{Read/Write }







Modes ^{Initial value 1}
1
1
1
0
0
0
0
5 to 7 _{Read/Write }



W
W
W
W
Reserved bits
Port 5 data direction 3 to 0
These bits select input or
output for port 5 pins
Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled): P5DDR values are fixed at 1
and cannot be modified. Port 5 functions as an address bus.
Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled): Following a reset, port 5 is
an input port. A pin in port 5 becomes an address output pin if the corresponding P5DDR bit is set
to 1, and an input port if this bit is cleared to 0.
Rev. 3.00 Sep 27, 2006 page 277 of 872
REJ09B0325-0300