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HD64F3048VTF8 Datasheet, PDF (260/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip | |||
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Section 8 DMA Controller
Address TA
Transfer
Address T B
Address BA
Address BB
Legend:
L A = initial setting of MARA
L B = initial setting of MARB
N = initial setting of ETCRA
TA = LA
BA = LA + SAIDE ⢠(â1)SAID ⢠(2DTSZ ⢠N â 1)
TB = LB
BB = LB + DAIDE ⢠(â1)DAID ⢠(2DTSZ ⢠N â 1)
Figure 8.8 Operation in Normal Mode
Transfers can be requested (activated) by an external request or auto-request. An auto-requested
transfer is activated by the register settings alone. The designated number of transfers are executed
automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC
releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus until the
transfers are completed, unless there is a bus request from a higher-priority bus master.
For the detailed settings see section 8.3.4, Data Transfer Control Registers (DTCR).
Rev. 3.00 Sep 27, 2006 page 232 of 872
REJ09B0325-0300
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