HD64F3048VTF8 Datasheet, PDF (145/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 5 Interrupt Controller
5.4.3 Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the
first instruction of the interrupt service routine is executed.
Table 5.5 Interrupt Response Time
External Memory
No. Item
1
Interrupt priority
decision
2
Maximum number of
states until end of
current instruction
3
Saving PC and CCR
to stack
4
Vector fetch
5
Instruction prefetch^*2
6
Internal processing^*3
On-Chip
Memory
2^*1
1 to 23^*5
8-Bit Bus
2 States
2^*1
3 States
2^*1
1 to 27^{*5 *6} 1 to 41^*6
4
8
12^*4
4
8
12^*4
4
8
12^*4
4
4
4
16-Bit Bus
2 States
2^*1
3 States
2^*1
1 to 23^*5 1 to 25^*5
4
6^*4
4
6^*4
4
6^*4
4
4
Total
19 to 41 31 to 57 43 to 83
19 to 41 25 to 49
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the
interrupt service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
5. Example for DIVXS.W Rs,ERd and MULXS.W Rs,ERd
6. Example for MOV.L @(d:24,ERs),ERd and MOV.L ERs,@(d:24,ERd)
Rev. 3.00 Sep 27, 2006 page 117 of 872
REJ09B0325-0300