HD64F3048VTF8 Datasheet, PDF (221/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 7 Refresh Controller
Contention between RTCOR Write and Compare Match
If a compare match occurs in the T₃ state of an RTCOR write cycle, writing takes priority and the
compare match signal is inhibited. See figure 7.22.
RTCOR write cycle by CPU
T₁
T₂
T₃
φ
Address bus
Internal
write signal
RTCNT
RTCNT address
N
N+1
RTCOR
Compare
match signal
N
M
RTCOR write data
Inhibited
Figure 7.22 Contention between RTCOR Write and Compare Match
RTCNT Operation at Internal Clock Source Switchover
Switching internal clock sources may cause RTCNT to increment, depending on the switchover
timing. Table 7.9 shows the relation between the time of the switchover (by writing to bits CKS2
to CKS0) and the operation of RTCNT.
The RTCNT input clock is generated from the internal clock source by detecting the falling edge
of the internal clock. If a switchover is made from a high clock source to a low clock source, as in
case No. 3 in table 7.9, the switchover will be regarded as a falling edge, an RTCNT clock pulse
will be generated, and RTCNT will be incremented.
Rev. 3.00 Sep 27, 2006 page 193 of 872
REJ09B0325-0300