HD64F3048VTF8 Datasheet, PDF (356/903 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip

Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.4 Register Configuration
Table 10.3 summarizes the ITU registers.
Table 10.3 ITU Registers
Channel
Common
0
1
Address^*1
H'FF60
H'FF61
H'FF62
H'FF63
H'FF90
H'FF91
H'FF64
H'FF65
H'FF66
H'FF67
H'FF68
H'FF69
H'FF6A
H'FF6B
H'FF6C
H'FF6D
H'FF6E
H'FF6F
H'FF70
H'FF71
H'FF72
H'FF73
H'FF74
H'FF75
H'FF76
H'FF77
Name
Timer start register
Timer synchro register
Timer mode register
Timer function control register
Timer output master enable register
Timer output control register
Timer control register 0
Timer I/O control register 0
Timer interrupt enable register 0
Timer status register 0
Timer counter 0 (high)
Timer counter 0 (low)
General register A0 (high)
General register A0 (low)
General register B0 (high)
General register B0 (low)
Timer control register 1
Timer I/O control register 1
Timer interrupt enable register 1
Timer status register 1
Timer counter 1 (high)
Timer counter 1 (low)
General register A1 (high)
General register A1 (low)
General register B1 (high)
General register B1 (low)
Abbre-
viation
TSTR
TSNC
TMDR
TFCR
TOER
TOCR
TCR0
TIOR0
TIER0
TSR0
TCNT0H
TCNT0L
GRA0H
GRA0L
GRB0H
GRB0L
TCR1
TIOR1
TIER1
TSR1
TCNT1H
TCNT1L
GRA1H
GRA1L
GRB1H
GRB1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)^*2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)^*2
R/W
R/W
R/W
R/W
R/W
R/W
Initial
Value
H'E0
H'E0
H'80
H'C0
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
Rev. 3.00 Sep 27, 2006 page 328 of 872
REJ09B0325-0300